Spatial light modulators are in wide use in display systems and are increasingly being used because they offer the benefit of high resolution while consuming lower power and being less bulky than conventional cathode ray tube (CRT) technology. One type of SLM display is the digital micro-mirror device (DMD). A DMD “chip” typically has an array of small reflective surfaces (mirrors) located on a semiconductor wafer to which electrical signals are applied to deflect the mirrors and change direction of the reflected light applied to the device. A DMD-based display system is created by projecting a beam of light to the device, selectively altering the orientations of the individual micro-mirrors with image data, and directly viewing or projecting the selected reflected portions to an image plane, such as a display screen. Each individual micro-mirror is individually addressable by an electronic signal and makes up one “display element” of the image. These micro-mirrors are often referred to as picture elements or “pixels,” which may or may not correlate directly to the pixels of an image. This use of terminology is typically clear from context, so long as it is understood that more than one pixel of the SLM array may be used to generate a pixel of the displayed image.
Generally, projecting an image from an array of DMD pixels is accomplished by loading memory cells connected to the pixels. Once each memory cell is loaded, the corresponding pixels are reset so that each one tilts in accordance with the ON or OFF state of the data in the memory cell. For example, to produce a bright spot in the projected image, the state of the pixel may be ON, such that the light from that pixel is directed out of the SLM and into a projection lens. Conversely, to produce a dark spot in the projected image, the state of the pixel may be OFF, such that the light is directed away from the projection lens.
Modulating the beam of light with a micro-mirror is used to vary the intensity of the reflected light, such as through Pulse-Width Modulation (PWM). Although the micro-mirrors can be moved relative to the bias voltage applied, the typical operation is a digital bi-stable mode in which the mirrors are fully deflected at any one time. Generating short pulses and varying the duration of the pulse to an image bit changes the time in which the portion of the image bit is reflected to the image plane versus the time the image bit is reflected away, therefore distributing the correct amount of light to the image plane.
The above-described pulse-width modulation techniques may be used to achieve varying levels of illumination in both black/white and color systems. For generating color images with SLMs, one approach is to use three DMDs: one for each additive primary color of red, green and blue (RGB). The light from corresponding pixels of each DMD is converged so that the viewer perceives the desired color. Another approach is to use a single DMD and a color wheel having sections of primary colors. Data for different colors is sequenced and synchronized to the color wheel so that the eye integrates sequential images into a continuous color image. Another approach uses two DMDs, with one switching between two colors and the other displaying a third color.
A PWM scheme is determined by using the display rate at which images are presented to the viewer and the number of intensity levels available by the display system. The display system rate is the time that the image frame is available for viewing. For example, a standard television signal is transmitted at 30 frames per second (fps), which is a frame time of 33.3 milliseconds. For a system having n bits of resolution, the image has 2n levels of intensity. Thus, if the system has four bits of intensity resolution, 16 levels of intensity can result. To create the perception of an intensity level in PWM systems, the frame is divided into equal time slices; each of which displays a quantized intensity. For a system having n bits of intensity resolution, the frame is divided into 2n−1 equal time slices. After the image element intensity is quantized, a black value, 0, would contain no intensity and be equivalent to zero time slices, while the maximum brightness level would have the display element on for all, or 2n−1, of the time slices.
An established method to get the time slices into a display frame is to format the data into “bit planes” where each bit plane corresponds to a bit weight of the intensity value. A system with four bits of intensity resolution (i.e., n=4) would have four bit planes and each bit plane would be weighted with an appropriate number of time slices. In an example binary weighted system, the 20 bit or least significant bit (LSB) would have one time slice, the 21 bit or next significant bit would have two time slices, the 22 bit or next significant bit would have four time slices, and the 23 bit or most significant bit (MSB) would have eight time slices. By displaying all of the bit planes within a frame, any of the capable intensity levels can be created in this weighted method. The quality of the image produced by the DMD generally increases as a function of the number of bit planes per pixel. Currently, 84 bit planes per pixel are seen as producing acceptably low image artifacts. In general, the more bit planes per pixel, the lower the number of artifacts.
Given the number of pixels in a typical DMD and given the number of bit planes required to deliver the desired color depth, a significant amount of memory is required to store the bit planes required to generate a particular frame. In fact, the largest amount of memory is needed for “formatting” the image into bit plane format the DMD requires. Fortunately, dynamic random access memory (DRAM), which is the type of memory desired for this use, is relatively inexpensive. Unfortunately, commercially available DRAM chips come in standard modules that have far more storage capacity than required to contain the bit planes. For example, today's commercially available external DRAM chips can store 512 Mbits; a typical DMD requires only about 100 Mbits.
Since DMDs need significantly less DRAM than commercially available modules offer, it seems reasonable to produce a single integrated circuit (IC) containing not only the image processing and control circuitry, but the image memory a DMD requires. However, commercially available DRAM chips are available at commodity prices. Even though the embedded DRAM would have a lower storage capacity (e.g., 100 Mbits) than the external DRAM, embedding DRAM with the image processing and control circuitry requires extra process steps and area, adding complexity, potentially reducing yield and therefore increasing the cost of the IC chip. Thus, it has not been cost-effective to embed the DRAM.
However, if the DMD's image memory size can be reduced, the DRAM can be reduced. At some point, it becomes cost-effective to embed the DRAM. Thus, what is needed in the art is a way to reduce DMD image memory size so embedding becomes economically feasible. More generally, what is needed in the art is a bit plane encoding/decoding system and method for reducing SLM image memory size.